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Altera_Forum's avatar
Altera_Forum
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16 years ago

Cyclone II glitch on clock

Hi, i have a cyclone II fpga. I'm using two asynchronus clock sources. These clocks are connected into the dedicated clock input of the chip (CLK0 and CLK2). CLK0 is much faster than CLK2 (100MH...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

So a workable code example is like this? 


PROCESS (CLOCK100)
BEGIN
if rising_edge (clock100) then
 clk2_b <= clk2;
 clk2_sync <= clk2_b;
end if;
END
PROCESS (CLOCK100, clk2_sync)
BEGIN
if rising_edge(clock100) then
last <= clk2_sync;
if (clk2_sync ='1' and last = '0') then
  clk2_enable = '1';
else
  clk2_enable = '0';
end if;
end if;
END PROCESS;
STATE_MACHINE: PROCESS (CLOCK100, clk2_enable)
 if rising_edge (clock100) then
   if clk2_enable = '1' then
     ...

Thank you