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It's not actually clear from your post,
how CLK2 "control a state machine". If it's actually the clock for the state machine process, then a ringing clock signal would be the most likely explanation. for the observed behaviour.
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It's the clock.
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I wonder, why you don't use an asynchronous edge detection for CLK2 instead? It would suppress all gliches smaller than 10 ns, if neccessary, a filter of multiple clock periodes could be added. This would also remove all synchronization problems between the clock domains.
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What is an asynchronus edge detection?
Is sampling CLK2 with CLK0? And what can i do to prevent metastability?
PROCESS (CLOCK100)
BEGIN
if rising_edge (clock100) then
clk2_b <= clk2;
clk2_sync <= clk2_b;
end if;
END
With this code clk2_sync is glitch free and not metastable?
Thank you
Honored Contributor
