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Honored Contributor
Honored ContributorCyclone II glitch on clock
Hi, i have a cyclone II fpga. I'm using two asynchronus clock sources. These clocks are connected into the dedicated clock input of the chip (CLK0 and CLK2). CLK0 is much faster than CLK2 (100MH...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- It's not actually clear from your post, how CLK2 "control a state machine". If it's actually the clock for the state machine process, then a ringing clock signal would be the most likely explanation. for the observed behaviour. --- Quote End --- It's the clock. --- Quote Start --- I wonder, why you don't use an asynchronous edge detection for CLK2 instead? It would suppress all gliches smaller than 10 ns, if neccessary, a filter of multiple clock periodes could be added. This would also remove all synchronization problems between the clock domains. --- Quote End --- What is an asynchronus edge detection? Is sampling CLK2 with CLK0? And what can i do to prevent metastability?
PROCESS (CLOCK100)
BEGIN
if rising_edge (clock100) then
clk2_b <= clk2;
clk2_sync <= clk2_b;
end if;
END
