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Altera_Forum
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16 years ago

Cyclone II glitch on clock

Hi, i have a cyclone II fpga. I'm using two asynchronus clock sources. These clocks are connected into the dedicated clock input of the chip (CLK0 and CLK2). CLK0 is much faster than CLK2 (100MH...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

The basic idea is to use CLK0 only and generate a clock enable from CLK2.

The below example uses a double synchronization register to consider for metastability, as suggested in the Quartus Software Handbook, although it's possibly not actually needed (the likelihood of metastable events is sometimes overestimated). 

process (clok0)
begin
  if rising_edge(clk0) then
    clk2_s1 <= clk2;
    clk2_s2 <= clk2_s1;
    clk2_prev <= clk2_s2;
    if clk2_prev = '0' and clk2_s2 = '1' then
    -- action on clk2 rising edge
    end if;
  end if;
end process;