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Altera_Forum
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16 years ago

Cyclone II glitch on clock

Hi, i have a cyclone II fpga. I'm using two asynchronus clock sources. These clocks are connected into the dedicated clock input of the chip (CLK0 and CLK2). CLK0 is much faster than CLK2 (100MH...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Hi, both are external clock.

CLK0 is generated by an oscillator, CLK2 by a microcontroller.

CLK2 is a not periodic square waveform. When microcontroller is ready to trasnfert data, pull the CLK2 line (is a enable bit). On the rising edge the data is trasnferred.