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Altera_Forum
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18 years ago

Cyclone II - losing configuration after power off

Hi.

I programe FPGA through JTAG (MSEL0, MSEL, nCE, DCLK0->GND; nCONFIG->VCC; nSTATUS, CONFIG_DONE->VCC through resistor). I'm using QuartusII (Device & Pin Options: Configuration scheme: PS - I can only choose PS or AS; ASD0, nCS0-configured as regular I/O; unused pins as output driving ground; In tools->options->Programmer "Halt on-chip configuration controller" checked).

The problem is that after turning power off and on again it looses its configuration. A few general pins I've checked goes high, and 1st(ASD0) and 2nd(nCS0) pins (which I use as a n input) turn to AS configuration mode.

I also noticed, that for very very short time (hardly noticable) after turning power on, the FPGA seems to be programmed in old configuration , but then it changes.

Have any idea what is wrong?

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    The FPGA is an SRAM based device.

    As such, when you turn off the power, it will lose the design you JTAG download to it!

    If this is a development board, it might then load a design that is in the onboard existing prom, not sure if that is your case here.

    It does not seem like there is anything wrong here.
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Hi.

    I'm just getting started withe FPGAs, so that is why I ask silly questions.

    I was sure, that what you loaded to FPGA is held. On other board with MAXII loaded configuration is held even if I turn the power off. And there is no prom on any of these two boards.

    Thank You for your answers
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Hi klombi

    1. First of all make sure that you use a .pof file and upload it to eprom (EPC, EPCS...etc)

    2. If you use a .sof it's normally that you lose a data after shut down, cause FPGA is a SRAM based device.

    Also try to check sinthesizer . As I remember there is check that enables conf.device ...look for it somewhere there..
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Max II devices are CPLD devices. (There is a section of the internal device that holds the programmed file so that after a power cycle, the part self loads the design file.)

    The FPGA you are using does not have such a storage device internal to the part.

    Either your board has an external serial storage device or an external parallel storage device and some other 'assisting device' like a CPLD to read the parallel device and load the FPGA, or there is a processor on board to load the FPGA.

    If you have none of these, then you cannot do what you are looking to do.

    The FPGA will lose configuration with every power cycle.

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