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Altera_Forum
Honored Contributor
18 years agoMax II devices are CPLD devices. (There is a section of the internal device that holds the programmed file so that after a power cycle, the part self loads the design file.)
The FPGA you are using does not have such a storage device internal to the part. Either your board has an external serial storage device or an external parallel storage device and some other 'assisting device' like a CPLD to read the parallel device and load the FPGA, or there is a processor on board to load the FPGA. If you have none of these, then you cannot do what you are looking to do. The FPGA will lose configuration with every power cycle. Avatar