Cyclone 10 LP PLL frequency far too low

Hi,
PLL parameters looks right. If you are not familiar with PLL setup, you can also implement altpll from IP catalog.
I would probably add locked output to monitor correct PLL operation.

Most likely reason to ge a very low output frequency is that PLL gets no valid input clock, either wrong pin connected or inappropriate logic level.

Hi,

I have checked the connections and the input clock is connected. I have routed the input clock and output to a test point and observed them on the scope. If that clock is valid, I'm not sure. Which parameter would I use to add locked output to the PLL? What do you mean by inappropriate logic level and how could I check for that?

Thank you

Hi,
specify PORT_LOCKED = "PORT_USED" and connect PLL245.locked respectively.

You can also route C30MHz to an output pin and check if it looks correct.

Hi,

I have done both of these. The PLL.locked signal is always low after the code upload is complete. The C30MHz looks exactly as expected.

I noticed these warnings:

Warning (332070): Port "PhiPLL" relative to the rising edge of clock "C30MHz" does not specify a max-fall output delay

Warning (332070): Port "PhiPLL" relative to the rising edge of clock "C30MHz" does not specify a max-rise output delay

Warning (332056): PLL cross checking found inconsistent PLL clock settings:

Warning (332056): Clock: PLL245MHz|auto_generated|pll1|clk[0] with master clock period: 32.550 found on PLL node: PLL245MHz|auto_generated|pll1|clk[0] does not match the master clock period requirement: 32.553

Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.

Critical Warning (332169): From PLL245MHz|auto_generated|pll1|clk[0] (Rise) to C30MHz (Rise) (setup and hold)

Critical Warning (332169): From PLL245MHz|auto_generated|pll1|clk[0] (Fall) to C30MHz (Rise) (setup and hold)

Critical Warning (332169): From PLL245MHz|auto_generated|pll1|clk[0] (Rise) to PLL245MHz|auto_generated|pll1|clk[0] (Rise) (setup and hold)

I'm not sure what they mean, but it seems that they are not errors that should cause the PLL to break. The Warning about the master clock period seems like it is related to the "INCLK0_INPUT_FREQUENCY" field, but I don't understand that field.

Hi,

We have found that the problem stemmed from a manufacturing error in our design that caused the PLL to not be properly powered. Thank you for your help finding this

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