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sambesse
New Contributor
New ContributorCyclone 10 LP PLL frequency far too low
Hello, I am working on a Cyclone 10 lp problem using an internal PLL. I'm using the above AHDL code to configure it. The expected output is 245Mhz, since it's a 30.72MHz input and a mu...
- Hi,
the small differences is frequency are obvious, you should be able to provide consistent values. However none of the quoted warnings is related to a fundamental problem that would prevent PLL function.
Some questions.
What's the reference clock source?
Is it a known working development board or custom design? In the latter case, are you sure that all hardware requirements, e.g. connection of PLL supply pins are met?
sambesseNew Contributor
New ContributorHi,
I have checked the connections and the input clock is connected. I have routed the input clock and output to a test point and observed them on the scope. If that clock is valid, I'm not sure. Which parameter would I use to add locked output to the PLL? What do you mean by inappropriate logic level and how could I check for that?
Thank you
