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sambesse
New Contributor
New ContributorCyclone 10 LP PLL frequency far too low
Hello, I am working on a Cyclone 10 lp problem using an internal PLL. I'm using the above AHDL code to configure it. The expected output is 245Mhz, since it's a 30.72MHz input and a mu...
- Hi,
the small differences is frequency are obvious, you should be able to provide consistent values. However none of the quoted warnings is related to a fundamental problem that would prevent PLL function.
Some questions.
What's the reference clock source?
Is it a known working development board or custom design? In the latter case, are you sure that all hardware requirements, e.g. connection of PLL supply pins are met?
FvM
Super Contributor
Super ContributorHi,
PLL parameters looks right. If you are not familiar with PLL setup, you can also implement altpll from IP catalog.
I would probably add locked output to monitor correct PLL operation.
Most likely reason to ge a very low output frequency is that PLL gets no valid input clock, either wrong pin connected or inappropriate logic level.
