Hi,
I have done both of these. The PLL.locked signal is always low after the code upload is complete. The C30MHz looks exactly as expected.
I noticed these warnings:
Warning (332070): Port "PhiPLL" relative to the rising edge of clock "C30MHz" does not specify a max-fall output delay
Warning (332070): Port "PhiPLL" relative to the rising edge of clock "C30MHz" does not specify a max-rise output delay
Warning (332056): PLL cross checking found inconsistent PLL clock settings:
Warning (332056): Clock: PLL245MHz|auto_generated|pll1|clk[0] with master clock period: 32.550 found on PLL node: PLL245MHz|auto_generated|pll1|clk[0] does not match the master clock period requirement: 32.553
Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
Critical Warning (332169): From PLL245MHz|auto_generated|pll1|clk[0] (Rise) to C30MHz (Rise) (setup and hold)
Critical Warning (332169): From PLL245MHz|auto_generated|pll1|clk[0] (Fall) to C30MHz (Rise) (setup and hold)
Critical Warning (332169): From PLL245MHz|auto_generated|pll1|clk[0] (Rise) to PLL245MHz|auto_generated|pll1|clk[0] (Rise) (setup and hold)
I'm not sure what they mean, but it seems that they are not errors that should cause the PLL to break. The Warning about the master clock period seems like it is related to the "INCLK0_INPUT_FREQUENCY" field, but I don't understand that field.
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