Cyclone 10 LP JTAG galvanic isolation
Hello,
Cyclone 10 design guideline says:
JTAG pins in the Intel Cyclone 10 LP device are powered up by VCCIO. However, you
may need to use VCCA in some cases.
• For devices using VCCIO of 2.5, 3.0, and 3.3 V, all I/O inputs must maintain a
maximum AC voltage of 4.1 V because JTAG pins do not have the internal PCI
clamping diodes to prevent voltage overshoot. You must power up the VCC of the
download cable with a 2.5-V supply from VCCA.
I have to ensure that voltage on the JTAG pins is not above 4,1V. My VCCIO is 3,3V.
In my case is implemented galvanic isolation on the board. (FPGA -> Isolator -> USB blaster).
Iam sure that 3,3V power rail on my board will not exceed 3,5V.
And the question is: Do I have to use voltage level shifter between FPGA and ISOLATOR for TDO, TCK and TMS pins from 3,3V to 2,5V?
Thanks!