Creating a bidirectional bus

I rewrote my code as:

You cannot use a "wire" in an "always" statement. It's a Verilog idiosyncranie.

input wire  USBBUS;
wire  USBBUS_i;
reg  USBBUS_o;
reg USBBUS_oe;
assign USBBUS_i = USBBUS;
assign USBBUS = USBBUS_oe == 1'b1 ? USBBUS_o : 8'hzz;
always @ (negedge clk) begin
if(write condition) begin
USBBUS_o <= outbus;
USBBUS_oe <= 1'b1;
end
else begin
USBBUS_o <= 8'hxx;
USBBUS_oe <= 1'b0;
end
if (read condition) begin
inbus <= USBBUS_i;
end
end

Thanks for your reply. I made the changes you suggested but now Quartus generates this error message: error (10219): verilog hdl continuous assignment error at testusb.v(353): object "inbus" on left-hand side of assignment must have a net type

 
input wire  USBBUS;
wire  USBBUS_i;
reg  USBBUS_o;
reg USBBUS_oe;
assign USBBUS_i = USBBUS;
assign USBBUS = USBBUS_oe == 1'b1 ? USBBUS_o : 8'hzz;   
 
wire  inbus_i;            //<<<<
assign inbus_i = inbus;     //<<<<
 
always @(negedge clk) begin
    if(TXE == 0) begin
        USBBUS_o <= outbus;
        USBBUS_oe <= 1'b1;
    end
    else begin
        USBBUS_o <= 8'hxx;        
        USBBUS_oe <= 1'b0;
    end
    if (RXF == 0) begin
        inbus_i <= USBBUS_i;    //<<<<
    end
end

To mention a simple thing, a bidirectional port has to be declared as inout.

Yes, the USBBUS pins are bidirectional. The signal inbus_i is not connected to any pins. Thanks for your reply.

My code was not meant to be complete; I had assumed you have a

reg  inbus

inbus was declared as a wire, it is the input to another module.

wire  USBBUS_i;
reg  USBBUS_o;
reg USBBUS_oe;
assign USBBUS_i = USBBUS;
assign USBBUS = USBBUS_oe == 1'b1 ? USBBUS_o : 8'hzz;
 
wire  inbus_w;
reg  inbus_r;
 
assign inbus_w = inbus;     // <<<<
assign inbus = inbus_r;     // <<<<
always @(negedge clk) begin
    if(TXE == 0) begin
        USBBUS_o <= outbus;
        USBBUS_oe <= 1'b1;
    end
    else begin
        USBBUS_o <= 8'hxx;
        USBBUS_oe <= 1'b0;
    end
    if (RXF == 0) begin
        inbus_r <= inbus;   // <<<<
    end
end

Please take note that my code was just "pseudo-code" to illustrate the concept.

I understand and that's very good advice. I have tested with MyHDL and ModelSim the module that deals with TXE and outbus and the module that deals with RXF and inbus. TXE and RXF are mutually exclusive in that only one can be true at any time. The code I am working on now, which requires the bidirectional bus, is additional test code to be downloaded into my device to determine if these modules will actually communicate with the USB device (FT245R). I'll write some code to test the bidirectional buffer stuff with ModelSim.

I wrote some test code to check out the above code in ModelSim (starter edition 6.6d) but got several errors I didn't understand. So I thought I would try something simpler. I found the bidirec code on Altera. I have attached the file containing my test code to this post.