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Altera_Forum
Honored Contributor
13 years agoI wrote some test code to check out the above code in ModelSim (starter edition 6.6d) but got several errors I didn't understand. So I thought I would try something simpler. I found the bidirec code on Altera. I have attached the file containing my test code to this post.
In ModelSim the code compiles OK. But when I click Start Simulation I get the following errors: "Illegal output or inout port connection for "port 'outp'". "Illegal output or inout port connection for "port 'bidir'". If all assignments to outp and bidir in module simBidir are commented the same errors are generated. If in module simBidir outp type is changed to a wire and the assignment to outp in STIMULUS is removed the illegal port connection error for outp is not generated when the simulation is started. But this cannot be done for bidir; at least, I assume an assignment to bidir should be permitted. What have I got wrong now?