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Altera_Forum
Honored Contributor
13 years agoinbus was declared as a wire, it is the input to another module.
With the changes below indicated by "<<<<" full compilation was successful. I haven't test it...
wire USBBUS_i;
reg USBBUS_o;
reg USBBUS_oe;
assign USBBUS_i = USBBUS;
assign USBBUS = USBBUS_oe == 1'b1 ? USBBUS_o : 8'hzz;
wire inbus_w;
reg inbus_r;
assign inbus_w = inbus; // <<<<
assign inbus = inbus_r; // <<<<
always @(negedge clk) begin
if(TXE == 0) begin
USBBUS_o <= outbus;
USBBUS_oe <= 1'b1;
end
else begin
USBBUS_o <= 8'hxx;
USBBUS_oe <= 1'b0;
end
if (RXF == 0) begin
inbus_r <= inbus; // <<<<
end
end