Creating a 3:1 Clock Mux

Question

hi, I am new here. I don't know if this is the correct place for my question.

So my setup: I have a 148.5MHz VCXO and a 67.5MHz VCXO clks coming into a Stratix II GX EP2SGX901508C3. Right now, I am using altpll to create 74.25Mhz clk from the 148.5MHz VCXO and using altpll to create a 27Mhz clk from the 67.5Mhz VCXO.

Because I am trying to do clock recovery depending on my signal's input, I added another altpll acting as a 2:1 clkmux. I am using the clk switch function. I have 74.25Mhz clk and 27Mhz clk as inputs and am selecting one as my output. All of this as been working fine.

Now, I am trying to add a third clk to this mux. A 67.5Mhz clk into this mux. But the clk switch function from altpll only does 2:1. How do I create a 3:1 clock mux? Any suggestions? Thanks!

altera_forum · Answer

Have you tried ALTCLKCTRL?  This should allow up to 4 clocks to be muxed.  Although, there are restrictions on the possible combinations of sources for the clocks.

altera_forum · Answer

I have tried using altclkctrl but i cannot make my project compile. I do not think I pass their restrictions because my 67.5Mhz VCXO clk is on a refclk pin not a clk pin.

altera_forum · Answer

Another way to switch between three clocks is to cascade two PLLs.  Of course, this can increase the jitter or otherwise impact the performance.

altera_forum · Answer

That is an interesting idea. Do you mean taking the my output (x) from the first PLL into a second PLL? The second PLL will have my 67.5Mhz clk and 'x' as input. But my question here is, since 'x' is either going to be 27MHz or 148MHz, what am I supposed to put as my frequency when creating this atlppll in megafunction?

altera_forum · Answer

You would need to enable dynamic PLL reconfiguration on the second PLL so that you can reconfigure it at runtime for the correct input frequency.

I am actually curious to see if anyone else responds with some other approaches. I have needed to mux 3 clocks before as well.

Forum Discussion

Creating a 3:1 Clock Mux

7 Replies

Recent Discussions

LVDS SERDES rx_inclock idle

Max10 Security Bit

Asynchronous FIFO and discontinuous write clock

Using Clocklock+Clockboost on EPF10K100GC503-3DX with Quartus 9.0SP2. How?

Timing Behavior of Remote Update IP After Reset on Cyclone 10 GX (10CX150YF672E5G)