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Altera_Forum
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16 years ago

Creating a 3:1 Clock Mux

hi, I am new here. I don't know if this is the correct place for my question. So my setup: I have a 148.5MHz VCXO and a 67.5MHz VCXO clks coming into a Stratix II GX EP2SGX901508C3. Right now, ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I have tried using altclkctrl but i cannot make my project compile. I do not think I pass their restrictions because my 67.5Mhz VCXO clk is on a refclk pin not a clk pin.