Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorCreating a 3:1 Clock Mux
hi, I am new here. I don't know if this is the correct place for my question. So my setup: I have a 148.5MHz VCXO and a 67.5MHz VCXO clks coming into a Stratix II GX EP2SGX901508C3. Right now, ...
Altera_ForumHonored Contributor
Honored ContributorThat is an interesting idea. Do you mean taking the my output (x) from the first PLL into a second PLL? The second PLL will have my 67.5Mhz clk and 'x' as input. But my question here is, since 'x' is either going to be 27MHz or 148MHz, what am I supposed to put as my frequency when creating this atlppll in megafunction?
