Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Creating a 3:1 Clock Mux

hi, I am new here. I don't know if this is the correct place for my question. So my setup: I have a 148.5MHz VCXO and a 67.5MHz VCXO clks coming into a Stratix II GX EP2SGX901508C3. Right now, ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I will have to go read more about this dynamic PLL reconfiguration. When I enable it, there are so many extra input and output pins, ie scanclk, scanread, scanwrite, scandata. I will have to figure out their parameters are.