Altera_Forum
Honored Contributor
Honored ContributorCreate own Avalon MM-Slave
Hi there
I'm trying to create my first Avalon MM-Slave which should be accessible through a NIOS II softcore. In the end I just want a MM-Slave which has a conduit input and output for connecting to my custom logic. I am using a very simple MM-Slave which I have found on the internet to test how the slave behaves and how I have to build up my own slave with my needs. The slave works so far and I'm basically able to read from and wirte to the slave. But there is something I do not understand: The component uses the following entity:entity system_cpu_serial_interface_2 is port(
-- Avalon Clock interface
clk : in std_logic;
-- Avalon Reset interface
reset : in std_logic;
-- Avalon-MM Slave interface
address : in std_logic_vector(1 downto 0);
read : in std_logic;
write : in std_logic;
readdata : out std_logic_vector(31 downto 0);
writedata : in std_logic_vector(31 downto 0)
);
end system_cpu_serial_interface_2;result = IORD_32DIRECT(SYSTEM_CPU_SERIAL_INTERFACE_2_0_BASE, 1);IOWR_32DIRECT(SYSTEM_CPU_SERIAL_INTERFACE_2_0_BASE, 2, 0xAAAAAAAA);
