--- Quote Start ---
Can you attach the RAM read-write logic used?
--- Quote End ---
Anand Raj, I'm not sure what RAM read-write logic you mean. Are you talking about the on-chip memory of the NIOS II? If yes, there was no explicit read-write logic generated by Qsys (see attached porject_overview_1.jpg). Or are you talking about the template I found on the internet (if yes then look at the attached file system_cpu_serial_interface_2.vhd)? Or does the avalon interconnect have a RAM for read- and write data (there are a lot of components generated for the interconne?
--- Quote Start ---
it may be because of that logic issue.Follow the timing diagram from below attachment
https://www.altera.com/en_us/pdfs/li...ug_ram_rom.pdf --- Quote End ---
I don't see the connection between my problem and the document you attached. Do you wanna say that I have a problem with a RAM or do you mean that there is a general timing issue with the Avalon bus?
--- Quote Start ---
(...) what have you set as the base address of this component?
--- Quote End ---
The base address of the component is 0x0008_1040
--- Quote Start ---
And since you're using Signal Tap, what does the address look like on the master side instead of the slave side?
--- Quote End ---
This was also my intention and I did also capture a shot where the master signals are included (see attachment st_master_signals.jpg). But for me it is pretty hard to debug on the master side, since I don't know the master in detail.
--- Quote Start ---
I doubt it would make a difference, but what happens if you use just IORD and IOWR instead of the 32DIRECT commands you used?
--- Quote End ---
This is it! It makes a difference! If I use the IORD and IOWR it works as expected. But whats the difference between IOWR and IOWR32DIRECT?
Honored Contributor
