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arik's avatar
arik
Icon for New Contributor rankNew Contributor
27 days ago

CPRI F-Tile Dynamic Reconfiguration

Hi,

I use the Q24.2 and have Agilex7 F-Series 014. 

I my design I use CPRI Phy over several of my FGTs. I generated the CPRI Phy IP to have 4 line rates (LRs) - LR8 (startup profile), LR7, LR5 & LR3. I want to change the CPRI LRs dynamically. To do this I followed the user guide (UG-20341 - F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide).

For example, if I want to change LR in the first transcever from LR8 (profile 1) to  LR3 (profile 4) I will do the follwing process:

  1. Reset the trancever phy - i_tx_rst_n &  i_rx_rst_n are set to 1'b0.
  2. Trigger DR to target profile 4:
    - avmm_write(32'h04, 32'h00040001)
    - avmm_write(32'h08, 32'h00008004)
    - avmm_write(32'h0, 32'h00000001)
  3. Changing the CPRI rate in the Phy Configuration to LR 3 - setting 2 to offset address 0x0 & 0x4
  4. Release the reset of the transcever phy - i_tx_rst_n &  i_rx_rst_n are set to 1'b1.

If I want to change the LR from LR3 to any other LR, I need to do the same procedure as described before but the start profile will be now 4.

The prblem is that I need to remember the last set profile each time I want to change the LR. This is very problematic since the CPU that perform and control the DR process need always to hold the profile state in its memory and if for example it crashes it should dig from its memory the last profile state after its recovery. Another problem is if the controller crashes in the middle of LR change, it cant guess the state of the current profile when it recovers.

To handle this, I saw in the in the UG that I can use the Recovery option. To do that, I need to synthesize the project after setting the Recovery enabled option in the Dynamic Reconfiguration Suite GUI.
For example, after changing from LR8 to LR3 I want to change back to LR8:

  1. Reset the trancever phy - i_tx_rst_n &  i_rx_rst_n are set to 1'b0.
  2.  Restore back to startup mode:
    - avmm_write(32'h04, 32'h00060001)
    - avmm_write(32'h0, 32'h00000001)
  3. Changing the CPRI rate in the Phy Configuration to LR 8 - setting 9 to offset address 0x0 & 0x4
  4. Release the reset of the transcever phy - i_tx_rst_n &  i_rx_rst_n are set to 1'b1.

I wasnt succeeded to do the recovery and I will appreciate if you tell me how to do it.

Regards,

Arik

 

Configuration

6 Replies

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    25 days ago

    Hi Arik,

     

    Thank you for filing this case and sharing the details. I appreciate your patience. Please allow me some time to review the information, and I’ll get back to you as soon as possible. 

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    25 days ago

    Hi Arik,

     

    Based on my understanding, you have an inquiry related to CPRI PHY dynamic reconfiguration. There does not appear to be any issue with the standard dynamic reconfiguration flow; however, when Recover Mode is enabled, the behavior does not seem to be as expected.

     

    I cross‑checked your register write sequence against the F‑Tile DR User Guide and did not observe any specific anomalies.

     

    To ensure we are aligned, could you please help clarify the following:

     

    1. When you mention that the recovery “wasn’t succeeded,” could you please elaborate on the exact behavior you observed? For example, are there any error indicators, status register values, or specific symptoms you are seeing?
    2. Have you had a chance to run a ModelSim simulation using a simple single‑channel test design? If so, would you mind sharing the test design with simulation files along with the steps required to reproduce the issue? This would greatly help facilitate further debugging.

     

    Please let me know if you have any concerns or questions. Thank you.

  • arik's avatar
    arik
    Icon for New Contributor rankNew Contributor
    21 days ago

    Hi,

    Thank you for your response.

    I did not create a simulation for the design, I work only with the Signal Tap.

    When I mentioned that the recovery wasn't successful meant that for example, if the startup LR is LR8 and the transceiver was in LR7, if I set the Recovery command to startup LR, I will expect that the transceiver will start to receive and transmit in LR8. However, all I receive is "garbage" in the rx_data in LR8.

    What is wrong with my process that was described in my previous message?

    • CheepinC_altera's avatar
      CheepinC_altera
      Icon for Regular Contributor rankRegular Contributor
      17 days ago

      Hi Arik,

       

      I have reviewed the high‑level steps you described in your previous note, and at this point I do not see any obvious anomalies from the flow itself.

       

      To help move the debugging process forward more efficiently, I would recommend running a Questasim functional simulation using the current design. This would allow us to observe the behavior in a controlled environment and check whether the same behavior can be reproduced during simulation.

       

      Starting with functional simulation can help isolate whether the issue is design‑ or flow‑related, before introducing additional variables from the hardware platform. This approach often makes it easier to narrow down the root cause and can significantly reduce overall debug time.

       

      Please let me know if you have any concerns.

       

      Thank you.

    • CheepinC_altera's avatar
      CheepinC_altera
      Icon for Regular Contributor rankRegular Contributor
      9 days ago

      Hi Arik,

       

      Just would like to follow up with you on my previous note. Please let me know if there is any concern. Thank you.