Forum Discussion
New ContributorCPRI F-Tile Dynamic Reconfiguration
New ContributorHi,
Thank you for your response.
I did not create a simulation for the design, I work only with the Signal Tap.
When I mentioned that the recovery wasn't successful meant that for example, if the startup LR is LR8 and the transceiver was in LR7, if I set the Recovery command to startup LR, I will expect that the transceiver will start to receive and transmit in LR8. However, all I receive is "garbage" in the rx_data in LR8.
What is wrong with my process that was described in my previous message?
Regular ContributorHi Arik,
I have reviewed the high‑level steps you described in your previous note, and at this point I do not see any obvious anomalies from the flow itself.
To help move the debugging process forward more efficiently, I would recommend running a Questasim functional simulation using the current design. This would allow us to observe the behavior in a controlled environment and check whether the same behavior can be reproduced during simulation.
Starting with functional simulation can help isolate whether the issue is design‑ or flow‑related, before introducing additional variables from the hardware platform. This approach often makes it easier to narrow down the root cause and can significantly reduce overall debug time.
Please let me know if you have any concerns.
Thank you.
