Converting Oscillator HCSL Output to SSTL_18

Question

I am designing a PCB with a MAX 10 (10M50DAF256) with DDR2 and the MAX 10 requires a SSTL_18 clock source. I found Renesas AN-891 online and it describes using a HCSL driver, series 0.1uF capacitors and resistor voltage divider network tied to VCC1V8 to convert to SSTL. Has anyone done this in their design? Will it work? I chose the Epson SG3225HBN to use. I really don't have the need or the room for a 1x8 CLK BUFFER IC with a SSTL output. Please advise.

fvm · Answer

You can select LVDS IO standard to receive HCSL clock at MAX10.

shaneh_fl · Answer

Thanks for the reply but I do require a differential SSTL_18 100MHz source since I am using DDR2. All assigned pins to Banks 5 and 6 are set to SSTL_18.  Also, VREF to both banks is 900mV.

fvm · Answer

Not clear what you want achieve. DDR IP expects that RAM clock is sourced by FPGA not an external oscillator.

shaneh_fl · Answer

I have the MAX 10 EVAL KIT and it uses a custom programmed Si5338A and one of its outputs is the CLK_DDR3_100 to the FPGA. I bring this into Platform Designer using a Clock Bridge IP and I am able to get the the DDR3 IP up and running with this clock source. So I am just trying to duplicate this with my DDR2 design on a custom PCB.The CLK_DDR3_100 differential outputs of the Si5338A-CUSTOM are tied to series 0.1uF caps and then are pulled up to VCC1V5 and down to GND with 2Kohm resistors which provide a reference of 750mV. After seeing Renesas AN-891 and knowing the MAX 10 requires at least 500mVpp for SSTL_18, I am assuming that the output of the Si5338A-CUSTOM is HCSL. I think my circuit will satisfy the differential SSTL_18 input requirement for the MAX 10. I am just wondering if anyone has done this with a discrete oscillator that has a HCSL output or can tell that this should work. I guess if it does not work as intended I can use a FPGA generated 100MHz PLL for the DDR2 IP. Thank you for replying to my posts.

fvm · Answer

Hi,thanks for referring to MAX10 FPGA Development Kit for clarification. I expect that respective capacitive coupling  will also work for differential SSTL-18 clock input. According to my knowledge, differential clock input uses always the same differential input buffer. Actual common mode range is larger and minimal differential input voltage smaller than SSTL spec suggests. The clock input will most likely work driven by HCSL without capacitive coupling.On the other hand, I don't see a purpose of having a separate clock source for DDR3 RAM IP. You'll preferably use an internal  PLL source with defined phase relation to other design clock domains.

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Converting Oscillator HCSL Output to SSTL_18

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