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shaneh_fl's avatar
shaneh_fl
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1 year ago

Converting Oscillator HCSL Output to SSTL_18

I am designing a PCB with a MAX 10 (10M50DAF256) with DDR2 and the MAX 10 requires a SSTL_18 clock source. I found Renesas AN-891 online and it describes using a HCSL driver, series 0.1uF capacitors ...
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FvM's avatar
FvM
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1 year ago
You can select LVDS IO standard to receive HCSL clock at MAX10.
  • shaneh_fl's avatar
    shaneh_fl
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    1 year ago

    Thanks for the reply but I do require a differential SSTL_18 100MHz source since I am using DDR2. All assigned pins to Banks 5 and 6 are set to SSTL_18. Also, VREF to both banks is 900mV.

    • FvM's avatar
      FvM
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      1 year ago
      Not clear what you want achieve. DDR IP expects that RAM clock is sourced by FPGA not an external oscillator.
      • shaneh_fl's avatar
        shaneh_fl
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        1 year ago

        I have the MAX 10 EVAL KIT and it uses a custom programmed Si5338A and one of its outputs is the CLK_DDR3_100 to the FPGA. I bring this into Platform Designer using a Clock Bridge IP and I am able to get the the DDR3 IP up and running with this clock source. So I am just trying to duplicate this with my DDR2 design on a custom PCB.

        The CLK_DDR3_100 differential outputs of the Si5338A-CUSTOM are tied to series 0.1uF caps and then are pulled up to VCC1V5 and down to GND with 2Kohm resistors which provide a reference of 750mV. After seeing Renesas AN-891 and knowing the MAX 10 requires at least 500mVpp for SSTL_18, I am assuming that the output of the Si5338A-CUSTOM is HCSL. I think my circuit will satisfy the differential SSTL_18 input requirement for the MAX 10. I am just wondering if anyone has done this with a discrete oscillator that has a HCSL output or can tell that this should work. I guess if it does not work as intended I can use a FPGA generated 100MHz PLL for the DDR2 IP. Thank you for replying to my posts.