Forum Discussion

shaneh_fl's avatar
shaneh_fl
Icon for New Contributor rankNew Contributor
1 year ago

Converting Oscillator HCSL Output to SSTL_18

I am designing a PCB with a MAX 10 (10M50DAF256) with DDR2 and the MAX 10 requires a SSTL_18 clock source. I found Renesas AN-891 online and it describes using a HCSL driver, series 0.1uF capacitors ...
Board Debug
FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
1 year ago

Hi,
other than assumed above, differential SSTL-18 input buffer seems to work differently from true differential inputs like LVDS.

There's this comment about differential SSTL-xx and HSTL-xx inputs in the handbook:
"The inputs treat differential inputs as two single-ended inputs and decode only one of them" ( Intel® MAX® 10 General Purpose I/O User Guide 683751 2022.10.31, p 7).

It's also stated in MAX10 datasheet: "Differential SSTL requires a VREF input."