New Contributor
Super ContributorHi,
thanks for referring to MAX10 FPGA Development Kit for clarification. I expect that respective capacitive coupling will also work for differential SSTL-18 clock input. According to my knowledge, differential clock input uses always the same differential input buffer. Actual common mode range is larger and minimal differential input voltage smaller than SSTL spec suggests. The clock input will most likely work driven by HCSL without capacitive coupling.
On the other hand, I don't see a purpose of having a separate clock source for DDR3 RAM IP. You'll preferably use an internal PLL source with defined phase relation to other design clock domains.
