New Contributor
Super ContributorHi,
I did a test on an existing board with LVDS input. I switched the IO-standard to differential SSTL-2 class I and supplied a variable VREF voltage. The circuit behaves as if CLK_P input is compared with VREF while CLK_N is ignored. Switching to single-ended SSTL-2 results in identical behaviour, also identical VREF margins. Seems like there's no difference between single-ended and differential SSTL for an input. Respectively required input swing is double the magnitude needed for a true differential input. You also need to care for input bias matching VREF.
A possible advantage of using differential over single ended SSTL is that charge injection to VREF node is cancelled, presuming there's a second input buffer connected to CLK_N.
