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Altera_Forum's avatar
Altera_Forum
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17 years ago

Connecting Altera FPGA to external Serializer/deserializer (LVDS)

Hello all;

I'm trying to connect Serializer/deserially

to FPGA. The reason is to transmitt or

receive high speed serial data. To transmitt

data, tclk from FPGA is required to supply to

serializer. The frequency for tclk is equal

to 10Mhz. The input transition time of tclk measured by occilloscop is equal to 10ns. According to datasheet, the max input transition time of tclk is equal to 6ns.

The LVDS low-to-high and high-to-low transition time are equal to 7.6ns respectively. According to datasheet, the max LVDS low-to-high and high-to-low transition time are equal to 0.4ns respectively.

Question:

Can i improve the input transition time of tclk by using Quartus II software??

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Sorry, but your hardware setup is completely unclear. I guess, that your measurements are at a LVDS output from FPGA to an external device. If so:

    - which FPGA family?

    - wich type of LVDS driver (I/O standard)?

    - which external receiver?

    - what kind of termination is involved?

    - how you are measuring the said data (probe, oscilloscope)?

    To my opinion, it's simply impossible to achieve > 1ns tr/tf with a correctly operated LVDS driver (any type, either Altera FPGA or external chips).
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Sorry confusing you.

    To answer your question, i'm using cyclone II FPGA. Anyway, let me describe the issue again. Let forgot the external Serializer/deserializer (LVDS).

    i'm trying to generate 10Mhz clk from cyclone II FPGA. I found out the low-to-high transition time and high-to-low transition time are equal to 7.6ns.

    Is there any way to get the fall/rise time less than 5ns???
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    The I/O standard and the termination is important as well. With terminated and impedance matched IO standards, as LVDS or SSTL, transition times are considerably below 1 ns. with others, depending on drive strength respectively driver impedance and load capacitance.

    Generally, I use low drive strength or add an external series termination for low and medum speed signals to reduce overshoot and EMI. In this case, some ns of transition time are expectable and mostly wanted.

    For a realistic measurement of signal transition times,high speed, low capacitance active probes or resistive probes are mandatory. If you see 7.6 ns at an FPGA output pin, I suspect a wrong circuit or an inapproriate measurement equipment.