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Altera_Forum
Honored Contributor
Honored ContributorConnecting Altera FPGA to external Serializer/deserializer (LVDS)
Hello all; I'm trying to connect Serializer/deserially to FPGA. The reason is to transmitt or receive high speed serial data. To transmitt data, tclk from FPGA is required to supply to ...
Altera_ForumHonored Contributor
Honored ContributorSorry confusing you.
To answer your question, i'm using cyclone II FPGA. Anyway, let me describe the issue again. Let forgot the external Serializer/deserializer (LVDS). i'm trying to generate 10Mhz clk from cyclone II FPGA. I found out the low-to-high transition time and high-to-low transition time are equal to 7.6ns. Is there any way to get the fall/rise time less than 5ns???
