Connecting Altera FPGA to external Serializer/deserializer (LVDS)

The I/O standard and the termination is important as well. With terminated and impedance matched IO standards, as LVDS or SSTL, transition times are considerably below 1 ns. with others, depending on drive strength respectively driver impedance and load capacitance.

Generally, I use low drive strength or add an external series termination for low and medum speed signals to reduce overshoot and EMI. In this case, some ns of transition time are expectable and mostly wanted.

For a realistic measurement of signal transition times,high speed, low capacitance active probes or resistive probes are mandatory. If you see 7.6 ns at an FPGA output pin, I suspect a wrong circuit or an inapproriate measurement equipment.