connect two pll in serial to get 250MHZ clock

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since this FPGA cannot generate more than 180 MHZ clock

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This is not the case. Where did you find this?

One PLL is all you need. Even the slowest speed grade should manage. Refer to Table 1–25. PLL Specifications in the cylcone iv datasheet (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-iv/cyiv-53001.pdf).

However, as flz47655 stated, driving logic in Cyclone IV at 250MHz is another matter. Keep it simple...

Cheers,

Alex

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I have a Cyclone IV E FPGA with a 50MHZ oscillator , since this FPGA cannot generate more than 180 MHZ clock, I decide to get 125MHZ clock from one altpll , using this 125MHZ and then connect to another altpll to get another 250MHZ cmos clock and output to outside world like ADC . Of course I got a critical warning after compiling , can I have this approach to get 250MHZ clock like this ?

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If you only want to generate clock to outside of the CIV, according to the datasheet, the max it can go is 472.5MHz directly to PLL clock output pin.