connect two pll in serial to get 250MHZ clock

--- Quote Start ---

since this FPGA cannot generate more than 180 MHZ clock

--- Quote End ---

This is not the case. Where did you find this?

One PLL is all you need. Even the slowest speed grade should manage. Refer to Table 1–25. PLL Specifications in the cylcone iv datasheet (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-iv/cyiv-53001.pdf).

However, as flz47655 stated, driving logic in Cyclone IV at 250MHz is another matter. Keep it simple...

Cheers,

Alex