configuring 2 FPGAs in PS mode

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I want to be able to reconfigure them by the CPU separately

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You need to treat them as completely separate devices, eg., all the PS control signals need to be separated.

If you need to have the devices configure in two-device PS mode at some times, and then in single device PS mode at other times, you can use tri-state buffers or bus-switches on the PS signals, and use the CPU to select the appropriate operating mode.

Feel free to post a diagram showing what you are trying to do, and forum members will take a look.

Cheers,

Dave

--- Quote Start ---

You need to treat them as completely separate devices, eg., all the PS control signals need to be separated.

If you need to have the devices configure in two-device PS mode at some times, and then in single device PS mode at other times, you can use tri-state buffers or bus-switches on the PS signals, and use the CPU to select the appropriate operating mode.

Feel free to post a diagram showing what you are trying to do, and forum members will take a look.

Cheers,

Dave

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Thanks Dave,

it is not clear for me why should I separate the DATA and DCLK signals? and even the nSTATUS and Config_done , as they are open drain according to my knowledge can stay connected together . Can you explain more broadly your recommendation.

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it is not clear for me why should I separate the DATA and DCLK signals? and even the nSTATUS and Config_done , as they are open drain according to my knowledge can stay connected together . Can you explain more broadly your recommendation.

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Ok.

1. DATA could be a common signal

2. DCLK could be a common signal, BUT you should buffer it, so that each FPGA gets a nice clean clock signal. Do not daisy chain the clock (transmission line reflections can occur, depending on layout)

3. nCONFIG should not be common, since then you cannot independently clear the configuration of the devices

4. nSTATUS should not be common, since when you pulse nCONFIG on one device, nSTATUS for that device will assert, and place the other FPGA in an error state

5. CONF_DONE should not be common, as holding this signal low can be used to delay the FPGA entering USER mode. When you pulse nCONFIG on one device, CONF_DONE for that device will assert, and its probably undefined as to what the other device in USER mode will do (bad things most likely!)

Ultimately you will want to look at your PCB layout. If the two FPGAs are separated, and you have enough I/O pins on your PS master, then having separate interfaces may make the PCB layout simpler.

Cheers,

Dave