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it is not clear for me why should I separate the DATA and DCLK signals? and even the nSTATUS and Config_done , as they are open drain according to my knowledge can stay connected together . Can you explain more broadly your recommendation.
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Ok.
1. DATA could be a common signal
2. DCLK could be a common signal, BUT you should buffer it, so that each FPGA gets a nice clean clock signal. Do not daisy chain the clock (transmission line reflections can occur, depending on layout)
3. nCONFIG should not be common, since then you cannot independently clear the configuration of the devices
4. nSTATUS should not be common, since when you pulse nCONFIG on one device, nSTATUS for that device will assert, and place the other FPGA in an error state
5. CONF_DONE should not be common, as holding this signal low can be used to delay the FPGA entering USER mode. When you pulse nCONFIG on one device, CONF_DONE for that device will assert, and its probably undefined as to what the other device in USER mode will do (bad things most likely!)
Ultimately you will want to look at your PCB layout. If the two FPGAs are separated, and you have enough I/O pins on your PS master, then having separate interfaces may make the PCB layout simpler.
Cheers,
Dave
Honored Contributor
