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Altera_Forum's avatar
Altera_Forum
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16 years ago

Config 1S25 using CPLD

Hi,all

I'm tring to use a CPLD to config EP1S25 in PS mode. I've see the datasheet and here's my promblem. When CONF_DONE goes high and config is done, do i need continue clkpulse on the DCLK pin befor INIT_DONE goes high? if so when INIT_DONE goes high , need the DCLK stop immediatly ? or is it ok to continue 1 or 2 cycles on DCLK pin?

thanks

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    The answer to the first question is yes (as far as I know), to the second is surely no. In multiple FPGA configurations schemes, DCLK can be shared between mutiple devices and is ignored before and after configuration.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    The only information i am aware about DCLK after INIT_DONE is that DCLK must not float and it doesn't matter if it stays 0 or 1