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Altera_Forum's avatar
Altera_Forum
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16 years ago

Conf_done Is Not Going High.

Dear All,

We have designed Stratix III(EP3SL340) FPGA development board.

With that I am facing strange problem.

We are using JTAG interface from Quartus by using USB Blaster to program the Stratix III FPGA.

Programmer says Programming is completed suceesfully.

But CONF_DONE is going high for a 100ms after that it is goin to low.

Under this condition & all the intended functionalities of the FPGA are working fine.

This is happening only to a particular sof file. Remainign all other .Sof files CONF_DONE is going high & permanently stays at Logic "1"

Did anybody faces this type of issue.

Any Idea what could be the reason.

Is there any tool specific option I need to look into this.

Best Regards,

Kalidoss

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    You may want to check over the schematic associated with your dev board, and the pinout of the particular design and make sure you don't have either of the following conditions:

    1: A pin is unassigned, and Quartus placed it on a pin associated with board reset, causing sporadic system resets.

    2: You have all unused pins defined as driving ground, and one is connected to board reset, or a power supply where it needs to be at a logic high.

    3: The board has a watch dog circuit that needs to be strobed, but you are not strobing it.

    Pete
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Hi Pete,

    Thanks for your valuable input.....

    I will provide few more inputs that will give some additional information on this issue..

    There is no change in the design for working & non working sof. The only different is these sof's are generated in different time with same project.

    Also we have set the the following options in the " Settings--> Device ---> Unused pins will be configured as input tristated."

    Will this above info gives any clue with respect to the the problems..

    Best Regards,

    Kalidoss
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Hi Kalidoss..

    My best guess is you have a pin that is unassigned that moves around from build to build, and occasionally causes issues.

    Look through the .pin file of a "Working" .sof and the broken .sof if you still have them, and see if you have any differences there.

    The other thing to look for is to see if you have any warnings of pin with no exact location.

    The weak pullup option mentioned above could also solve the issue if it's due to just a "floating" output causing the issue.

    Pete