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Altera_Forum
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16 years ago

Conf_done Is Not Going High.

Dear All, We have designed Stratix III(EP3SL340) FPGA development board. With that I am facing strange problem. We are using JTAG interface from Quartus by using USB Blaster to prog...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

You may want to check over the schematic associated with your dev board, and the pinout of the particular design and make sure you don't have either of the following conditions:

1: A pin is unassigned, and Quartus placed it on a pin associated with board reset, causing sporadic system resets.

2: You have all unused pins defined as driving ground, and one is connected to board reset, or a power supply where it needs to be at a logic high.

3: The board has a watch dog circuit that needs to be strobed, but you are not strobing it.

Pete