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Altera_Forum
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16 years ago

Conf_done Is Not Going High.

Dear All, We have designed Stratix III(EP3SL340) FPGA development board. With that I am facing strange problem. We are using JTAG interface from Quartus by using USB Blaster to prog...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Hi Pete,

Thanks for your valuable input.....

I will provide few more inputs that will give some additional information on this issue..

There is no change in the design for working & non working sof. The only different is these sof's are generated in different time with same project.

Also we have set the the following options in the " Settings--> Device ---> Unused pins will be configured as input tristated."

Will this above info gives any clue with respect to the the problems..

Best Regards,

Kalidoss