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Honored Contributor
Honored Contributorconcatenation on wire
Hi all,
I did a simple experiments regarding concatenation on wire, below is the verilog code. // file : le_count_experiment.v// date : 17 dec 2010
// author : ty6
// to experiment le count of various operator
module le_count_experiment (//input
in1,
in2,
out,
clk,
ld,
rst);
//parameter
parameter data_width = 4;
//input
input [data_width-1:0] in1;
input [data_width-1:0] in2;
input clk;
input rst;
input ld;
//output
output [data_width-1:0] out;
//wire
wire [9*data_width-1:0] reg_in/* synthesis keep */;
wire [9*data_width-1:0] reg_out/* synthesis keep */;
//assigment
assign reg_in = {in1, in2};
assign out = reg_out[data_width-1:0];
regn register (.d(reg_in),
.clk(clk),
.en(ld),
.rst(rst),
.q(reg_out));
defparam register.data_width = 9*data_width;
endmodule I define reg_in as wire (9*4 = 36 bits) and concatenate both inputs in1 and in2 (both 4 bits) to become 8bits. However, i got a compilation warning: warning: design contains 4 input pin(s) that do not drive logic
warning (15610): no output dependent on input pin "in1[0]"
warning (15610): no output dependent on input pin "in1[1]"
warning (15610): no output dependent on input pin "in1[2]"
warning (15610): no output dependent on input pin "in1[3]" and the simulation result shows that only in2 is assigned to reg_in, and reg_in is only 4bits wire in simulation. Anyone has any idea why concatenation on wire does not work? Thanks and Regards, ty6
