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Altera_Forum
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15 years ago

concatenation on wire

Hi all, I did a simple experiments regarding concatenation on wire, below is the verilog code. // file : le_count_experiment.v // date : 17 dec 2010 // author : ty6 // to experiment ...
Altera_Forum's avatar
Altera_Forum
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15 years ago

assign reg_in = {in1, in2};

I would expect a compilation error, because the expression width doesn't match in assignment of reg_in. I'm not sure, if you can expect a particular result in case of an illegal assignment.