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Altera_Forum
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15 years ago

concatenation on wire

Hi all, I did a simple experiments regarding concatenation on wire, below is the verilog code. // file : le_count_experiment.v // date : 17 dec 2010 // author : ty6 // to experiment ...
Altera_Forum's avatar
Altera_Forum
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15 years ago

Here's an example, lets say we had this:

wire A, B, C, D;

wire [3:0] aBUS;

assign A = 1'b1;

assign B = 1'b1;

assign C = 1'b0;

assign D = 1'b1;

assign aBUS = {A, B, C, D};

The signal "aBUS" would have the value 4'b1101 fed into it. In other words the width of the concatenated signal is the sum of the widths of all the signals you are concatenating.