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Altera_Forum
Honored Contributor
Honored Contributorconcatenation on wire
Hi all, I did a simple experiments regarding concatenation on wire, below is the verilog code. // file : le_count_experiment.v // date : 17 dec 2010 // author : ty6 // to experiment ...
Altera_ForumHonored Contributor
Honored ContributorThere is nothing wrong with the result.
If you trace the path in reverse order. out is 4 bit thus it can take only 4 bits as an input, source to out is 36 bit from reg_in but it will take only least significant 4 bits. The reg_in gets 8 bits as an input but final o/p is only 4 bit reaching to the port thus compiler removes upper 4 bits and leaves only lsb 4 bits , i.e. in2. Thus in1 is reported to be removed, since it doesnt drive any logic.
