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Altera_Forum
Honored Contributor
15 years agoconcatenation on wire
Hi all, I did a simple experiments regarding concatenation on wire, below is the verilog code. // file : le_count_experiment.v // date : 17 dec 2010 // author : ty6 // to experiment ...
Altera_Forum
Honored Contributor
15 years agomeans that reg_in, in1 and in2 must be same width?