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Altera_Forum
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15 years ago

concatenation on wire

Hi all, I did a simple experiments regarding concatenation on wire, below is the verilog code. // file : le_count_experiment.v // date : 17 dec 2010 // author : ty6 // to experiment ...
Altera_Forum's avatar
Altera_Forum
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15 years ago

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means that reg_in, in1 and in2 must be same width?

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No it's not required. I thought, it would be the case, because VHDL wouldn't allow this assignment, Verilog however does. But the explanation is much easier. In1 is simply assigned to the part of reg_in, that's never read. You have to double the width of reg_out to see the in1 data.

I'm not absolutely sure, if you know, what a concatenation is? With DATA_WIDTH = 4, it creates a bit-vector of length 8. If you only read the lower 4 bits, in1 is ignored.