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Altera_Forum's avatar
Altera_Forum
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17 years ago

Components and FSM in my VHDL code...

Hi,

I am doing a project using VHDL for my Altera chip. In my project, I have a few components such as incoming signal detection and FSM for outputting PWM signals etc.

I have to keep on using FSM for outputting PWM signals. That means I can not hold it or stop it. Then, how can I run other components simultaneously? For example, when the FSM is running, I also need to keep the component of "Incoming signals detection" running, how can I do that?

Thanks a lot!

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    If your input detection function and FSM are designed properly concurrently then it should work. Input detection doesn't wait for FSM and the FSM process doesn't wait, or does it?

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Hi, Kaz,

    Thanks for your reply.

    How could I design the FSM and the input detection component concurrently?

    FSM should not wait as it has its own timing restraint in outputting PWMs. Meanwhile the incoming signal detection component has to run in real-time as well....If I keep the FSM, then how can the code take care of the other components running simultaneouly?

    Also, I plan to have another FSM for other usage, any recommendation of how to handle the two FSM or more FSM in one package of code?

    Many thanks, again!
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Hi,

    You don't run these functions sequentially. Hardware is inherently concurrent unless you design to wait. The FSM and any clocked process only waits for clk edge. all clocked registers everywhere do thier transitions at the same time. So leave the burden to hardware. This is not software which runs sequentially from one instruction to next...

    You can add several FSMs to your module by declaring new type and signal names for your states

    type Mystates1 is (s0,s1...);

    signal state1 : Mystates1;

    type Mystates2 is (M0,M1...);

    signal state2 : Mystates2;

    type Mystates3 is (N0,N1...);

    signal state3 : Mystates3;

    and so on ... then code for each FSM as usual independantly.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Kaz,

    Thank you so much for your help and patience! I will try it right now.

    Thanks a lot!!:-)
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    As a further note, it is common to think of vhdl as software because it is.

    but vhdl ends up in hardware configuration. It is helpful to think of three elements here:

    software (e.g. vhdl or exe for nios)

    firmware(sof/pof including nios itself)

    hardware(the dead platform)

    In vhdl itself some of the work is meant to be general purpose programming. These are issues that are settled at compile time e.g. a loop statement is used to tell compiler that you don't want to write all statements and that you want the compiler to insert them...remember also non-synthesisable code for test benches...so vhdl is a mixed environment.

    all processes are concurrent with each other, so are all combinatorial assignments. but statements within a process are executed sequentially by the compiler to work out a hardware that you decribe.