Components and FSM in my VHDL code...

As a further note, it is common to think of vhdl as software because it is.

but vhdl ends up in hardware configuration. It is helpful to think of three elements here:

software (e.g. vhdl or exe for nios)

firmware(sof/pof including nios itself)

hardware(the dead platform)

In vhdl itself some of the work is meant to be general purpose programming. These are issues that are settled at compile time e.g. a loop statement is used to tell compiler that you don't want to write all statements and that you want the compiler to insert them...remember also non-synthesisable code for test benches...so vhdl is a mixed environment.

all processes are concurrent with each other, so are all combinatorial assignments. but statements within a process are executed sequentially by the compiler to work out a hardware that you decribe.