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Altera_Forum
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17 years ago

Components and FSM in my VHDL code...

Hi, I am doing a project using VHDL for my Altera chip. In my project, I have a few components such as incoming signal detection and FSM for outputting PWM signals etc. I have to keep on ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Hi, Kaz,

Thanks for your reply.

How could I design the FSM and the input detection component concurrently?

FSM should not wait as it has its own timing restraint in outputting PWMs. Meanwhile the incoming signal detection component has to run in real-time as well....If I keep the FSM, then how can the code take care of the other components running simultaneouly?

Also, I plan to have another FSM for other usage, any recommendation of how to handle the two FSM or more FSM in one package of code?

Many thanks, again!