Components and FSM in my VHDL code...

Hi,

You don't run these functions sequentially. Hardware is inherently concurrent unless you design to wait. The FSM and any clocked process only waits for clk edge. all clocked registers everywhere do thier transitions at the same time. So leave the burden to hardware. This is not software which runs sequentially from one instruction to next...

You can add several FSMs to your module by declaring new type and signal names for your states

type Mystates1 is (s0,s1...);

signal state1 : Mystates1;

type Mystates2 is (M0,M1...);

signal state2 : Mystates2;

type Mystates3 is (N0,N1...);

signal state3 : Mystates3;

and so on ... then code for each FSM as usual independantly.