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Altera_Forum's avatar
Altera_Forum
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11 years ago

Clocked process triggered by pulse signal (VHDL question)

What I would like to do is to execute a clocked process whenever the rising edge of a pulse arrives. Here is my code: 


process (pulse, clk)
variable newTrigger: std_logic:='0';
variable cnt: integer range -1 to 32;
begin
if rising_edge(pulse) then
newTrigger:='1';
end if;
if newTrigger='1' then
newTrigger:='0';
cnt:=32;
elsif rising_edge(clk) then
if cnt<0 then
blahblah
else
cnt:=cnt-1;
blahblah
end if;
end process;

I heard that there should be only one clock for one process, but my code seemed to have two clocks. Is my above code OK to work in hardware? If no, is there any other method to achieve what I need? Thanks guys.

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Using a "rising_edge" function basically uses the specified signal as a clock. In an FPGA you can only use 1 clock per process.

    But your code is rather confusing, because according to your code, even if you could use two clocks, as soon as there was a rising edge of pulse, newTrigger is instantly set back to '0'. So how did you expect it to work?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    --- Quote Start ---

    Using a "rising_edge" function basically uses the specified signal as a clock. In an FPGA you can only use 1 clock per process.

    But your code is rather confusing, because according to your code, even if you could use two clocks, as soon as there was a rising edge of pulse, newTrigger is instantly set back to '0'. So how did you expect it to work?

    --- Quote End ---

    What I want to do is that the variable "cnt" can be set to 32 once after a rising edge of pulse arrives. Setting newTrigger instantly back to 0 is to ensure that "cnt" is set to 32 only once.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Then you need to synchronise the pulse with the clock

    do an edge detect (register the s_pulse - synchronised pulse - and compare the registered version with current version).

    When you detect an edge - then reset the cnt

    PS. Why are you using variables? If you're a beignner, I highly suggest you use only signals.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    --- Quote Start ---

    Then you need to synchronise the pulse with the clock

    do an edge detect (register the s_pulse - synchronised pulse - and compare the registered version with current version).

    When you detect an edge - then reset the cnt

    PS. Why are you using variables? If you're a beignner, I highly suggest you use only signals.

    --- Quote End ---

    Is there any specific reason of using signals only instead of variables? Thanks.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Variables have behaviour that can create combinatorial logic, and can also be confusing when toy check the behaviour computed to the actual hardware. From this put out view it it's much more obvious what will happen when you use signals. So signals are much safer for beginners and much easier for other engineers can understand