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Altera_Forum
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10 years ago

Clocked process triggered by pulse signal (VHDL question)

What I would like to do is to execute a clocked process whenever the rising edge of a pulse arrives. Here is my code: process (pulse, clk) variable newTrigger: std_logic:='0'; variable cnt: int...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Variables have behaviour that can create combinatorial logic, and can also be confusing when toy check the behaviour computed to the actual hardware. From this put out view it it's much more obvious what will happen when you use signals. So signals are much safer for beginners and much easier for other engineers can understand